The present invention relates to a method for fabricating a capacitor of a semiconductor device, and more specifically, to a method for fabricating a capacitor of a semiconductor device by forming a silicon nanowire structure having a large aspect ratio using a porous anodic alumina structure and applying the silicon nanowire structure to a bottom electrode, thereby obtaining a capacitor having secured capacitance.
Due to rapid distribution of information media such as computers, the development of process equipment and process techniques is required to manufacture a high-integrated semiconductor memory device that operates at high speeds with large capacities.
A memory cell of a DRAM device includes a transistor and a capacitor. The transistor serves as a switch for transmitting information. The capacitor is configured to store data. Generally, the capacitor includes conductive materials to supply current which are arranged in a given space. The conductive materials are insulated by an insulating material having a specific dielectric constant. The capacitance of the capacitor is proportional to the effective area of the capacitor and the dielectric constant of the conductive material used as a dielectric material, and inversely proportional to a space between the two conductive materials.
In order to fabricate a capacitor with secured capacitance, studies to increase the height of the lower storage electrode of the capacitor and the effective area like the surface area of the capacitor are continually being researched. Recently, a cylinder-type capacitor, with an internal area as well as external area, used as a node area has been applied in the manufacturing process of semiconductor devices.
Meanwhile, due to improvement in the integration of the semiconductor memory device and reduction in the effective area of the semiconductor device, it is necessary to develop a capacitor structure suitable for high-integrated memory devices so that the capacitance of the capacitor may be maintained over a given set-standard.
Methods for fabricating a capacitor includes: (1) a method for increasing a lower electrode area vertically while a two-dimensional size is limited by increasing a thickness of a capacitor oxide film by a stack process or an etched depth of a lower silicon substrate by a trench process; (2) a method for decreasing a formation thickness of a dielectric film or using a high dielectric constant (high-K) material, for example, a conductive material having a high dielectric constant; or (3) a method for growing a meta-phase silicon (MPS) at inner sidewalls of a capacitor pattern to form a concavo-convex structure over the surface of the capacitor or increasing the effective area in a capacitor structure using polysilicon as upper and lower electrodes to improve capacitance. The high dielectric constant material used in the method (2) includes a metal having a large atomic weight like hafnium (Hf), zirconium (Zr), tantalum (Ta) or strontium (St) or metal oxides obtained from combinations thereof.
However, as the semiconductor memory device becomes more integrated, when the methods (1) and (3) are performed, the aspect ratio of the lower electrode is increased due to increase of the thickness of the capacitor oxide film, so that it is difficult to perform a patterning process using a photo-lithography process. As a result, since it is difficult to etch the capacitor oxide film with a uniform type, the number of defective proportion can be high after the patterning process. Also, in the method (2), when the high dielectric constant materials are deposited with several Å thickness (1^−10 m) by an atomic layer deposition (ALD) method, the process difficulty is increased so that it is difficult to deposit the high dielectric material uniformly. As a result, leakage current through the dielectric film is generated, which results in loss of charges stored in the lower electrode and information loss.